![]() ![]() Conversely, a “reset” state inhibits input K so that the flip-flop acts as if J=1 and K=0 when in fact both are 1. ![]() On the next clock pulse, the outputs will switch or “toggle” from set (Q=1 and Q’=0) to reset (Q=0 and Q’=1). ![]() Now what happens when both J and K inputs are 1 !!!!!īecause of the selective inhibiting action of those 3-input AND gates, a “set” state inhibits input J so that the flip-flop acts as if J=0 while K=1 when in fact both are 1. If the circuit is “set,” the J input is inhibited by the 0 status of Q’ through the lower AND gate if the circuit is “reset,” the K input is inhibited by the 0 status of Q through the upper AND gate. In other words, the two inputs are interlocked, so that they cannot both be activated simultaneously. And permit the K input to have effect only when the circuit is set i.e. Now from the above diagram it is clear that, this allows the J input to have effect only when the circuit is reset, i.e. And the third input of each gate receives feedback from the Q and Q’ outputs. The old two-input AND gates of the S-R flip-flop have been replaced with 3-input AND gates. The circuit diagram of the J-K Flip-flop is shown in fig.2. Outputs Q and Q’ are the usual normal and complementary outputs. The input labeled CLK is the clock input. The inputs labeled J and K are the data inputs ( which used to be S and R inputs in S-R Flip-flop). ![]()
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